Huawei's Tao Law: Logic Folding Drives New Chip Path

China’s chip sector has taken a distinct path from the West and achieved breakthroughs despite nine years of US pressure, says CCTV-affiliated account Yu Yuan Tan Tian. The piece argues US attempts to use extreme pressure to halt China’s tech progress have failed and that cooperation could still benefit both sides. It highlights rising domestic strengths: mature process capacity scaling, record integrated circuit exports above one trillion yuan, progress on “neck‑choking” technologies, and localized etching and packaging. At the 2026 International Circuits and Systems symposium, Huawei semiconductor head He Tingbo introduced a new industry principle, the “tau (韬) law,” and said Huawei has designed and produced 381 chips in six years and will ship a new Kirin phone chip using logic folding this fall.

At ISCAS 2026 Huawei board member and semiconductor head He Tingbo unveiled the “Tau (韬) law” and revealed that Kirin 2026 used LogicFolding — a multi-layer vertical partitioning of digital, analog and memory — to boost performance without advanced lithography. Tests on Kirin 2026 show transistor density rising from 155 to 238 MTr/mm² within one generation, 41% core energy-efficiency gains, ~13% peak clock uplift and major SRAM and interconnect improvements. Huawei says Kirin 2027 is already at silicon stage and maps a roadmap through 2035 where full-scale multi-layer folding and mixed bonding enable higher densities and >4GHz cores; Ascend (昇腾) AI accelerators (910C→950→990) will adopt chiplets, 2.5D and 3D folding to multiply hardware integration by 2035.

At ISC A 2026, Huawei board member and Semiconductor Business President He Tingbo announced a new industry guideline called the “Tao (τ) law,” marking China’s first proposed semiconductor development principle. He outlined Huawei’s 2026–2035 roadmap: continued transistor density increases and higher clock frequencies as exploratory technologies mature into products, with Huawei’s Kirin mobile chips maintaining performance parity with an alternative development path. He emphasized that Huawei’s solution—including techniques like “logic folding”—is viable for sustained performance gains, and previewed Kirin 2026 improvements (53.5% transistor density increase and >3GHz peak). The speech signals Huawei’s intent to push domestic advanced SoC capabilities amid global chip competition.

At ISCAS 2026 Huawei director and semiconductor head He Tingbo said Huawei made major efforts since 2020 to bring smartphone chips back to market. After last year’s Kirin 9030 Pro hit a performance “saturation” point, Huawei applied a new τ (tau) law—shifting from geometric to time scaling—and introduced LogicFolding and other innovations to compress signal latency and boost transistor density. The upcoming Kirin 2026 uses a novel free-logic design expanded from single to double layers, delivering step-change performance gains that conventional process scaling alone cannot achieve. Huawei expects many innovations to reach production chips from 2027 onward, impacting mobile SoC performance, energy efficiency, and system-level architectures.

Huawei announced at the 2026 International Conference on Circuits and Systems that it will ship a new Kirin smartphone chip this autumn that fully adopts "logic folding" technology, claiming substantial performance gains. Board member and head of semiconductor business He Tingbo also unveiled a new "Tao (τ) law," noting Huawei has designed and mass-produced 381 chips in six years and projects continued transistor-density improvements through 2031. The new Kirin is expected to debut in the Mate 90 flagship series, aligning with Huawei's typical autumn Mate launch cadence and earlier leaks about large dual-layer OLED displays for Mate 90 variants. The update signals Huawei pushing advanced chip techniques amid its consumer flagship roadmap.

Huawei unveiled a new semiconductor principle called the "Tao (τ) Law" at the 2026 International Conference on Circuits and Systems, proposing "time scaling" instead of traditional geometric scaling to boost chip performance. Presented by Huawei board member and semiconductor head He Tingbo, the law focuses on reducing system time constants via techniques like logic folding to compress signal propagation delay, enabling higher effective transistor density without relying on lithographic node shrink. Huawei says it has designed and mass-produced 381 chips under this approach over six years and will ship a new Kirin SoC using full logic-folding later this year. Huawei projects that by 2031 Tao-based chips will achieve transistor-density parity with a 1.4 nm process, and calls for global collaboration.

Huawei has formally introduced a new semiconductor guiding principle called the “Tao (τ) Law” at the 2026 International Symposium on Circuits and Systems in Shanghai. He Tingbo, Huawei board member and president of its semiconductor division, presented the law during a keynote titled “Exploring and Practicing New Paths in Semiconductors.” Huawei says the τ Law underpins six years of work that produced 381 chip designs now in mass production, and that it enabled a forthcoming Kirin smartphone chip due this autumn that fully adopts logic folding to substantially boost performance. The announcement signals China’s attempt to set new, industry-level design approaches amid global semiconductor competition.