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Researchers have reverse-engineered the microcode of Intel’s 1980 8087 floating-point co-processor, revealing a surprisingly complex microarchitecture behind seemingly simple instructions. Using die photography and microscopic analysis, they mapped 1,648 micro-instructions and dissected the microcode ROM, engine, datapath and register file (two temporaries and an eight-register stack with tag bits). A detailed look at the FXCH register-exchange routine shows how many micro-steps were needed for data movement and control, while broader findings explain how microcode implemented transcendental functions, precision handling and stack control. The work illuminates early FPU design choices that shaped later floating-point standards and processor implementations.
This reverse-engineering of the 8087 microcode exposes the low-level design choices that shaped early FPUs and modern floating-point behavior, informing how microarchitecture and microcode trade-offs impact performance and correctness. Tech professionals working on compilers, emulation, hardware design, or verification can use these findings to better model legacy behavior and avoid subtle numerical or compatibility pitfalls.
Dossier last updated: 2026-05-31 04:16:54
Microcode inside the Intel 8087 floating-point chip: register exchange
A reverse-engineering deep dive examines the Intel 8087 floating-point coprocessor’s microcode, focusing on the FXCH (floating-point exchange) instruction. The Opcode Collective imaged a die from the 40-pin DIP 8087 and mapped its central microcode ROM (1,648 sixteen-bit micro-instructions), microcode engine, and datapath (16-bit exponent, 64-bit significand). The article shows how seemingly simple instructions like FXCH require a 14-microinstruction sequence, details the chip’s two temporary and eight stack registers with tag bits, and outlines micro-instruction types (transfers, shifts, adder/subtractor loops, arithmetic controls, far jumps/calls). The analysis reveals the 8087’s complex, ad hoc microcode design and documents low-level implementation of early IEEE floating-point behavior.
The article analyzes reverse-engineered microcode inside Intel's 1980 8087 floating-point co-processor, spotlighting the surprisingly elaborate implementation of the FXCH (floating-point exchange) instruction. Using die photographs and a microscope, the author and the Opcode Collective map the chip's 1648 16-bit micro-instructions, the microcode ROM, microcode engine, and the datapath (16-bit exponent, 64-bit fraction). The piece explains the register file—two temporary and eight stack registers with tag bits—and the stack-control logic. It outlines micro-instruction formats (transfer, shift, adder/subtractor, arithmetic control, jumps/calls) and emphasizes how even simple-looking instructions require many micro-steps, illustrating early processor microarchitecture and the intricacy of floating-point co-processor design.
Intel's 8087 floating-point co-processor, introduced in 1980, dramatically sped up floating-point math—up to 100× faster—and helped establish the floating-point standards used in modern CPUs. The article examines the 8087's internal microcode, the low-level routines that implement complex functions like square roots, tangents, and exponentials, and highlights a specific mechanism: register exchange. By dissecting these microinstructions, the author reveals how the 8087 managed precision, instruction sequencing, and data movement inside the chip. Understanding this microcode sheds light on historical design choices that influenced subsequent FPU implementations and the evolution of IEEE floating-point practices in hardware and system software.