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Researchers reconstructed the Intel 80386’s microcode by extracting a 94,720-bit ROM from high-resolution die images and turning it into readable micro-operations. Combining image processing, AI-assisted automation, die-trace contributions, and manual analysis, they mapped μ-op layout, field boundaries, and 215 microcode entry points tied to specific instructions and variants. The team also decoded instruction-decoder and protection-test PLAs and revealed interfaces to hardware accelerators like multiply/divide, barrel shifter, and protection units. Their work shows how the 80386 shifts functions into dedicated hardware to improve per-cycle performance and illuminates legacy x86 microarchitecture design choices.
Recovering the 80386 microcode from die images reveals undocumented microarchitecture decisions and interfaces, informing CPU design, retrocomputing, and hardware security analysis. Tech professionals can apply the methods to analyze legacy and modern chips, audit firmware, and enable accurate FPGA reproductions.
Dossier last updated: 2026-05-23 16:14:37
Open-source z386 reconstructs an Intel 80386-class CPU on FPGA driven by recovered original microcode, and it can now boot DOS 6/7, run protected-mode programs (DOS/4GW, DOS/32A), and run games like Doom. Built in the spirit of z8086, z386 recreates enough of the original 386 so the 2,560-entry microcode ROM and other legacy structures (paging TLB, barrel shifter, Protection PLA) can be reused, while taking FPGA-friendly shortcuts (DSP blocks, a 16 KB 4-way L1 cache). Compared with ao486, z386 is smaller in HDL size and resources and performs like a fast ~70MHz cached 386/low-end 486. The project documents instruction prefetch, decode, microcode sequencing, cache design, testing, and bring-up lessons, making it useful for CPU archaeology, FPGA CPU design, and retro-computing.
z386 is an open-source FPGA implementation of an Intel 80386-class CPU that reuses recovered original Intel microcode to drive a reconstructed microarchitecture. The project now boots MS-DOS 6/7, runs protected-mode DOS programs (DOS/4GW, DOS/32A), and plays games such as Doom and Cannon Fodder, achieving performance comparable to a fast ~70MHz 386 or low-end 486. Compared with ao486, z386 has fewer lines of code, lower FPGA resource usage, and a slightly lower clock and graphics throughput. It preserves many original 386 structures (microcode ROM, TLB, barrel shifter, protection PLA) while adopting FPGA-friendly elements like a 16 KB 4-way L1 cache and DSP-based multiply/divide. This installment explains execution pipeline components including prefetch, decode and microcode integration.
Researchers extracted and disassembled the Intel 80386 CPU microcode from high-resolution die images, turning a 94,720-bit ROM dump into readable micro-operations. The effort combined image processing, AI-assisted automation, manual analysis, and die-trace work (including contributions from Ken Shirriff and others) to map μ-op layout, field boundaries, instruction entry points, and interfaces to hardware accelerators like multiply/divide, barrel shifter, and protection-test units. They decoded the instruction decoder PLAs and linked 215 microcode entry points to 80386 instructions, revealing how the chip offloads many algorithms to dedicated hardware for per-cycle speed. The work sheds light on microarchitecture design and legacy x86 implementation details.
Researchers extracted and disassembled the Intel 80386 microcode from high-resolution die images, turning a 94,720-bit ROM into intelligible µ‑ops. Using image processing, AI-assisted automation, die traces from Ken Shirriff, and manual analysis, the team reconstructed microcode layout, fields, instruction boundaries, and interfaces to hardware accelerators (multiply/divide, barrel shifter, protection unit). They also decoded the instruction decoder PLAs and protection-test PLA, mapping 215 microcode entry points (up from 60 in the 8086) to specific 80386 instructions and variants (register vs memory handling). The work reveals how the 80386 uses extra transistors to move functionality from microcode into faster hardware, improving per-cycle performance.