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New measurements highlight how “split locks” on x86-64—atomic operations that cross a cache-line boundary—can become a major performance hazard on modern Intel and AMD CPUs. Tests show they can trigger hardware fallbacks like bus locks, sharply increasing cross-core latency from tens of nanoseconds to hundreds of nanoseconds or even microseconds, while cutting memory performance beyond L2 and slowing real workloads. Linux’s split-lock detection and mitigation can trap these events and add throttling, but the underlying disruption remains significant. The impact varies by microarchitecture, cache topology, and cluster boundaries, underscoring the need for compilers and software to avoid misaligned atomics.
On April 13, 1992, Cyrix debuted its 486SLC CPU. Cyrix didn’t have its own fabrication plants so they relied on other chipmakers, such as SGS Thomson and Texas Instruments, to manufacture the chips. Part of the agreement allowed TI to The post Cyrix 486SLC CPU: Introduced April 13,1992 appeared first on The Silicon Underground .
Investigating Split Locks on x86-64
Chester Lam tested “split locks” — atomic operations that straddle two cache lines — on recent x86-64 CPUs and found they cause severe latency and cross-core disruption. Modern Intel and AMD CPUs can trap split locks and Linux enables mitigation by detecting them and inserting delays, but the hardware fallback (bus locks) still degrades performance dramatically. Benchmarks across Intel Arrow Lake and AMD Zen systems show split locks can raise core-to-core latency from tens of nanoseconds to hundreds of nanoseconds or microseconds, halve memory access performance past L2, and significantly slow real workloads like Geekbench photo filtering. Impact depends on microarchitecture, cache hierarchy, and cluster boundaries; some L2 configurations are less affected. The findings matter for multithreaded software, compilers, and OS mitigations that aim to avoid or detect split-lock-induced noisy-neighbor effects.
Investigating Split Locks on x86-64